View CY7C1442V33-200BZC_6776361.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

1m x 36 / 2m x 18 / 512k x 72 pipelined sram cy7c1440v33 cy7c1442v33 cy7c1446v33 preliminary cypress semiconductor corporation ? 3901 north first street san jose ca 95134 408-943-2600 document #: 38-05184 rev. ** revised april 8, 2002 440v33 features ? fast clock speed: 300, 250, 200, and 167 mhz provide high-performance 3-1-1-1 access rate fast access time: 2.3, 2.7, 3.0 and 3.5 ns optimal for depth expansion single 3.3v ?5% and +5% power supply v dd separate v ddq for 3.3v or 2.5v common data inputs and data outputs byte write enable and global write control chip enable for address pipeline address, data, and control registers internally self-timed write cycle burst control pins (interleaved or linear burst se- quence) automatic power-down for portable applications high-density, high-speed packages jtag boundary scan for bga packaging version available in 119-bump bg,165-ball fbga package and 100-pin tqfp packages (cy7c1440v33 and cy7c1442v33) 209 fbga package for cy7c1446v33 functional description the cypress synchronous burst sram family employs high-speed, low-power cmos designs using advanced sin- gle-layer polysilicon, triple-layer metal technology. each mem- ory cell consists of six transistors. the cy7c1440v33, cy7c1442v33, and cy7c1446v33 srams integrate 1,048,576 x 36 / 2,097,152 x18 and 524,288 x 72 sram cells with advanced synchronous peripheral cir- cuitry and a 2-bit counter for internal burst operation. all syn- chronous inputs are gated by registers controlled by a posi- tive-edge-triggered clock input (clk). the synchronous inputs include all addresses, all data inputs, address-pipelin- ing chip enable (ce ), burst control inputs (adsc , adsp , and adv ), write enables (bw a, bw b, bw c, bw d and bwe ), and global write (gw ). asynchronous inputs include the output enable (oe ) and burst mode control (mode). the data (dq a,b,c,d ) and the data parity (dp a,b,c,d ) outputs, enabled by oe , are also asynchro- nous. dq a,b,c,d and dp a,b,c,d apply to cy7c1440v33, dq a,b,c,d,e,f,g,h and dp a,b,c,d,e,f,g,h apply to cy7c1446v33 and dq a,b and dp a,b apply to cy7c1442v33. a, b, c, d, e, f, g, h each are 8 bits wide in the case of dq and 1 bit wide in the case of dp. addresses and chip enables are registered with either ad- dress status processor (adsp ) or address status controller (adsc ) input pins. subsequent burst addresses can be inter- nally generated as controlled by the burst advance pin (adv ). address, data inputs, and write controls are registered on-chip to initiate self-timed write cycle. write cycles can be one to four bytes wide as controlled by the write control inputs. indi- vidual byte write allows individual bytes to be written. bw a controls dqa and dpa. bw b controls dq b and dp b . bw c con- trols dqc and dpd. bw d controls dq and dpd. bw e controls dqe and dpe. bw f controls dqf and dpf. bw g controls dqg and dpg. bw h controls dqh and dph. bw a, bw b, bw c, bw d, bw e, bw f, bw g and bw h can be active only with bwe being low. gw being low causes all bytes to be written. write pass-through capability allows written data available at the output for the immediately next read cycle. this device also incorporates a pipelined enable circuit for easy depth ex- pansion without penalizing system performance. all inputs and outputs of the cy7c1440v33, cy7c1442v33 and the cy7c1446v33 are jedec standard jesd8-5 com- patible. selection guide cy7c1440v33 cy7c1442v33 cy7c1446v33 -300 cy7c1440v33 cy7c1442v33 cy7c1446v33 -250 cy7c1440v33 cy7c1442v33 cy7c1446v33 -200 cy7c1440v33 cy7c1442v33 cy7c1446v33 -167 maximum access time (ns) 2.2 2.4 3.1 3.5 maximum operating current (ma) com ? l tbd tbd tbd tbd maximum cmos standby current (ma) tbd tbd tbd tbd
preliminary cy7c1440v33 cy7c1442v33 cy7c1446v33 document #: 38-05184 rev. ** page 2 of 35 logic block diagram cy7c1440v33 - 1m x 36 cy7c1442v33 - 2m x 18 clk adv adsc a [19:0] gw bwe bw d bw c bw b bw a ce 1 ce 3 ce 2 oe zz burst counter address register output registers input registers 1m x36 memory array clk clk q 0 q 1 q d ce ce clr sleep control 36 36 20 18 18 20 (a [1;0] ) 2 mode adsp dq a,b,c,d dp a,b,c,d dq d , dp d bytewrite registers dq dq c , dp c bytewrite registers dq dq dq b , dp b bytewrite registers dq a , dp a bytewrite registers dq enable ce register dq enable delay register dq clk adv adsc a [20:0] gw bwe bw b bw a ce 1 ce 3 ce 2 oe zz burst counter address register output registers input registers memory array clk clk q 0 q 1 q d ce ce clr sleep control 18 18 21 19 19 21 (a [1;0] ) 2 mode adsp dq a,b dp a,b dq b , dp b bytewrite registers dq dq a , dp a bytewrite registers dq enable ce register dq enable delay register dq ce 2m x 18
preliminary cy7c1440v33 cy7c1442v33 cy7c1446v33 document #: 38-05184 rev. ** page 3 of 35 cy7c1446v33 - 512k x72 clk adv adsc a [18:0] gw bwe bw h bw g bw f bw e ce 1 ce 3 ce 2 oe zz burst counter address register output registers input registers 512kx72 memory array clk clk q 0 q 1 q d ce ce clr sleep control 72 72 19 17 17 19 (a [1;0] ) 2 mode adsp dq a,b,c,d,e,f,g,h dp a,b,c,d,e,f,g,h dq h , dp h bytewrite registers dq dq g , dp g bytewrite registers dq dq dq f , dp f bytewrite registers dq e , dp e bytewrite registers dq enable ce register dq enable delay register dq bw d bw c bw b bw a dq c , dp c bytewrite registers dq dq dq b , dp b bytewrite registers dq a , dp a bytewrite registers dq dq d , dp d bytewrite registers dq
preliminary cy7c1440v33 cy7c1442v33 cy7c1446v33 document #: 38-05184 rev. ** page 4 of 35 pin configurations a a a a a 1 a 0 v ss v dd a a a a a a a a a nc nc v ddq v ssq nc dpa dqa dqa v ssq v ddq dqa dqa v ss nc v dd zz dqa dqa v ddq v ssq dqa dqa nc nc v ssq v ddq nc nc nc nc nc nc v ddq v ssq nc nc dqb dqb v ssq v ddq dqb dqb v dd nc v ss dqb dqb v ddq v ssq dqb dqb dpb nc v ssq v ddq nc nc nc a a ce 1 ce 2 nc nc bwb bwa ce 3 v dd v ss clk gw bwe oe adsc adsp adv a a 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 mode cy7c1442 (2m x 18) nc a a a a a 1 a 0 a v ss v dd a a a a a a a a a dqpb dqb dqb v ddq v ssq dqb dqb dqb dqb v ssq v ddq dqb dqb v ss nc v dd zz dqa dqa v ddq v ssq dqa dqa dqa dqa v ssq v ddq dqa dqa dqpa dqpc dqc dqc v ddq v ssq dqc dqc dqc dqc v ssq v ddq dqc dqc v dd nc v ss dqd dqd v ddq v ssq dqd dqd dqd dqd v ssq v ddq dqd dqd dqpd a a ce 1 ce 2 bwd bwc bwb bwa ce 3 v dd v ss clk gw bwe oe adsc adsp adv a a 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 mode cy7c1440 (1m x 36) nc a 100-pin tqfp (top view) 72m 72m a
preliminary cy7c1440v33 cy7c1442v33 cy7c1446v33 document #: 38-05184 rev. ** page 5 of 35 pin configurations (continued) 2 3 4 5 6 7 1 a b c d e f g h j k l m n p r t u v ddq nc nc dqpc dqc dqd dqc dqd a a a a adsp v ddq a dqc v ddq dqc v ddq v ddq v ddq dqd dqd nc nc v ddq v dd clk v dd v ss v ss v ss v ss v ss v ss v ss v ss nc nc nc nc tdo tck tdi tms a 72m nc v ddq v ddq v ddq a aa a a a a a a a a a0 a1 dqa dqc dqa dqa dqa dqb dqb dqb dqb dqb dqb dqb dqa dqa dqa dqa dqb v dd dqc dqc dqc v dd dqd dqd dqd dqd adsc nc ce 1 oe adv gw v ss v ss v ss v ss v ss v ss v ss v ss dqpa mode dqpd dqpb bwb bwc nc v dd nc bwa nc bwe bwd zz 234567 1 a b c d e f g h j k l m n p r t u v ddq nc nc nc dqb dqb dqb dqb a a a a adsp v ddq a nc v ddq nc v ddq v ddq v ddq nc nc nc 72m v ddq v dd clk v dd v ss v ss v ss v ss v ss v ss v ss v ss nc nc nc nc tdo tck tdi tms a a nc v ddq v ddq v ddq a aa a a a a a a a a a0 a1 dqa dqb nc nc dqa nc dqa dqa nc nc dqa nc dqa nc dqa nc dqa v dd nc dqb nc v dd dqb nc dqb nc adsc nc ce 1 oe adv gw v ss v ss v ss v ss v ss v ss v ss v ss nc mode dqpb dqpa v ss bwb nc v dd nc bw a nc bwe v ss zz cy7c1442v33 (2m x 18) cy7c1440v33 (1m x 36) a a
preliminary cy7c1440v33 cy7c1442v33 cy7c1446v33 document #: 38-05184 rev. ** page 6 of 35 pin configurations (continued) cy7c1440v33 (1m x 36) - 11 x 15 fbga 165-ball bump fbga cy7c1442v33 (2m x 18) - 11 x 15 fbga 234567 1 a b c d e f g h j k l m n p r tdo nc nc nc nc dpb nc dqb ace 1 nc ce 3 bw bbwe ace 2 nc dqb dqb mode nc dqb dqb nc nc nc a 72m v ddq nc bw aclk gw v ss v ss v ss v ss v ddq v ss v dd v ss v ss v ss a v ss v ss v ss v ss v ddq v ddq nc v ddq v ddq v ddq v ddq a a v dd v ss v dd v ss v ss v ddq v dd v ss v dd v ss v dd v ss v ss v ss v dd v dd v ss v dd v ss v ss nc tck a0 v ss atdi atms dqb v ss nc v ss dqb nc v ss v ss v ss v ss v ss v ss v ss a1 dqb nc nc nc v ddq v ss 891011 a adv a adsc a oe adsp aa v ss v ddq nc dpa v ddq v dd nc dqa dqa nc nc nc dqa nc v dd v ddq v dd v ddq dqa v dd nc v dd nc v dd v ddq dqa v ddq v dd v dd v ddq v dd v ddq nc v ddq a a v ss aa aa dqa nc nc zz dqa nc nc dqa a v ddq 234567 1 a b c d e f g h j k l m n p r tdo nc nc dpc dqc dpd nc dqd ace 1 bw bce 3 bw cbwe ace 2 dqc dqd dqd mode nc dqc dqc dqd dqd dqd a 72m v ddq bw dbw aclk gw v ss v ss v ss v ss v ddq v ss v dd v ss v ss v ss a v ss v ss v ss v ss v ddq v ddq nc v ddq v ddq v ddq v ddq a a v dd v ss v dd v ss v ss v ddq v dd v ss v dd v ss v dd v ss v ss v ss v dd v dd v ss v dd v ss v ss nc tck a0 v ss atdi atms dqc v ss dqc v ss dqc dqc v ss v ss v ss v ss v ss v ss v ss a1 dqd dqd nc nc v ddq v ss 891011 a adv a adsc nc oe adsp aa v ss v ddq nc dpb v ddq v dd dqb dqb dqb nc dqb nc dqa dqa v dd v ddq v dd v ddq dqb v dd nc v dd dqa v dd v ddq dqa v ddq v dd v dd v ddq v dd v ddq dqa v ddq a a v ss aa aa dqb dqb dqb zz dqa dqa dpa dqa a v ddq
preliminary cy7c1440v33 cy7c1442v33 cy7c1446v33 document #: 38-05184 rev. ** page 7 of 35 pin configurations (continued) a b c d e f g h j k l m n p r t u v w 123456 789 11 10 dqg dqg dqg dqg dqg dqg dqg dqg dqc dqc dqc dqc nc dpg dqh dqh dqh dqh dqd dqd dqd dqd dpd dpc dqc dqc dqc dqc nc dqh dqh dqh dqh dph dqd dqd dqd dqd dqb dqb dqb dqb dqb dqb dqb dqb dqf dqf dqf dqf nc dpf dqa dqa dqa dqa dqe dqe dqe dqe dpa dpb dqf dqf dqf dqf nc dqa dqa dqa dqa dpe dqe dqe dqe dqe aadsp adv a nc nc nc a a a aaa aaaa1 a0 aa a aa a nc nc nc nc nc nc bws b bws f bws e bws a bws c bws g bws d bws h tms tdi tdo tck nc nc mode nc cen v ss nc clk nc v ss v dd v dd v dd v dd v dd v dd v dd v dd v dd v dd v dd v dd v dd v ss v ss v ss v ss v ss v ss v ss v ss nc v dd nc oe ce 3 ce 1 ce 2 adsc gw v ss v ss v ss v ss v ss v ss v ss zz v ss v ss v ss v ss nc v ddq v ss v ss nc v ss v ssq v ss v ss v ss v ss nc v ss v ddq v ddq v ddq v ddq v ddq nc v ddq v ddq v ddq v ddq nc v ddq v ddq v ddq v ddq nc v ddq v ddq v ddq v ddq v ddq v ddq v ddq v ddq v ddq v ddq cy7c1446 (512k x72) pin definitions name i/o description a0 a1 a input- synchronous address inputs used to select one of the address locations. sampled at the rising edge of the clk if adsp or adsc is active low, and ce 1, ce 2 , and ce 3 are sampled active. a [1:0] feed the two-bit counter. bwa bwb bwc bwd bwe bwf bwg bwh input- synchronous byte write select inputs, active low. qualified with bwe to conduct byte writes to the sram. sampled on the rising edge of clk. gw input- synchronous global write enable input, active low. when asserted low on the rising edge of clk, a global write is conducted (all bytes are written, regardless of the values on bw a,b,c,d,e,f,g,h and bwe ). bwe input- synchronous byte write enable input, active low. sampled on the rising edge of clk. this signal must be asserted low to conduct a byte write.
preliminary cy7c1440v33 cy7c1442v33 cy7c1446v33 document #: 38-05184 rev. ** page 8 of 35 clk input-clock clock input. used to capture all synchronous inputs to the device. also used to increment the burst counter when adv is asserted low, during a burst operation. ce 1 input- synchronous chip enable 1 input, active low. sampled on the rising edge of clk. used in conjunction with ce 2 and ce 3 to select/deselect the device. adsp is ig- nored if ce 1 is high. ce 2 input- synchronous chip enable 2 input, active high. sampled on the rising edge of clk. used in conjunction with ce 1 and ce 3 to select/deselect the device. (tqfp only) ce 3 input- synchronous chip enable 3 input, active low. sampled on the rising edge of clk. used in conjunction with ce 1 and ce 2 to select/deselect the device. (tqfp only) oe input- asynchronous output enable, asynchronous input, active low. controls the direction of the i/o pins. when low, the i/o pins behave as outputs. when deasserted high, i/o pins are three-stated, and act as input data pins. oe is masked during the first clock of a read cycle when emerging from a deselected state. adv input- synchronous advance input signal, sampled on the rising edge of clk. when asserted, it automatically increments the address in a burst cycle. adsp input- synchronous address strobe from processor, sampled on the rising edge of clk. when asserted low, a is captured in the address registers. a [1:0] are also loaded into the burst counter. when adsp and adsc are both asserted, only adsp is recognized. asdp is ignored when ce 1 is deasserted high. adsc input- synchronous address strobe from controller, sampled on the rising edge of clk. when asserted low, a [x:0] is captured in the address registers. a [1:0] are also loaded into the burst counter. when adsp and adsc are both asserted, only adsp is recognized. mode input- static selects burst order. when tied to gnd selects linear burst sequence. when tied to v ddq or left floating selects interleaved burst sequence. this is a strap pin and should remain static during device operation. zz input- asynchronous zz ? sleep ? input. this active high input places the device in a non-time critical ? sleep ? condition with data integrity preserved.this pin can also be left as a nc dqa, dpa dqb, dpb dqc, dpc dqd, dpd dqe, dpe dqf, dpf dqg, dpg dqh, dph i/o- synchronous bidirectional data i/o lines. as inputs, they feed into an on-chip data register that is triggered by the rising edge of clk. as outputs, they deliver the data contained in the memory location specified by a during the previous clock rise of the read cycle. the direction of the pins is controlled by oe . when oe is asserted low, the pins behave as outputs. when high, dqx and dpx are placed in a three-state condition. dq a,b,c,d,e,f,g, and h are 8 bits wide. dp a,b,c,d,e,f,g, and h are 1 bit wide. tdo jtag serial output synchronous serial data-out to the jtag circuit. delivers data on the negative edge of tck. (bga only) this pin can be left as a nc if jtag is not used. tdi jtag serial input synchronous serial data-in to the jtag circuit. sampled on the rising edge of tck. (bga only) this pin can be left as a nc if jtag is not used. tms tes t m o de s el e ct synchronous this pin controls the test access port state machine. sampled on the rising edge of tck. (bga only) this pin can be left as a nc if jtag is not used. pin definitions (continued) name i/o description
preliminary cy7c1440v33 cy7c1442v33 cy7c1446v33 document #: 38-05184 rev. ** page 9 of 35 tck jtag serial clock serial clock to the jtag circuit. (bga only) this pin can be left as a nc if jtag is not used. v dd power supply power supply inputs to the core of the device. should be connected to 3.3v ? 5% +10% power supply. v ss ground ground for the core of the device. should be connected to ground of the sys- tem. v ddq i/o power supply power supply for the i/o circuitry. should be connected to a 1.71 (min.) to v dd (max.) v ssq i/o ground ground for the i/o circuitry. should be connected to ground of the system. 72m no connects. reserved for address expansion. nc - no connects. pin definitions (continued) name i/o description
preliminary cy7c1440v33 cy7c1442v33 cy7c1446v33 document #: 38-05184 rev. ** page 10 of 35 introduction functional overview all synchronous inputs pass through input registers controlled by the rising edge of the clock. all data outputs pass through output registers controlled by the rising edge of the clock. max- imum access delay from the clock rise (t co ) is 2.2 ns (300-mhz device). the cy7c1440v33/cy7c1442v33/cy7c1446v33 support secondary cache in systems utilizing either a linear or inter- leaved burst sequence. the interleaved burst order supports pentium ? and i486 processors. the linear burst sequence is suited for processors that utilize a linear burst sequence. the burst order is user selectable, and is determined by sampling the mode input. accesses can be initiated with either the pro- cessor address strobe (adsp ) or the controller address strobe (adsc ). address advancement through the burst se- quence is controlled by the adv input. a two-bit on-chip wrap- around burst counter captures the first address in a burst se- quence and automatically increments the address for the rest of the burst access. byte write operations are qualified with the byte write enable (bwe ) and byte write select (bw a,b,c,d for cy7c1440v33, bw a,b for cy7c1442v33, and bw a,b,c,d,e,f,g,h for cy7c1446v33) inputs. a global write enable (gw ) overrides all byte write inputs and writes data to all four bytes. all writes are simplified with on-chip synchronous self-timed write cir- cuitry. synchronous chip selects (ce 1 , ce 2 , ce 3 for tqfp/ ce 1 for bga) and an asynchronous output enable (oe ) provide for easy bank selection and output three-state control. adsp is ignored if ce 1 is high. single read accesses this access is initiated when the following conditions are sat- isfied at clock rise: (1) adsp or adsc is asserted low, (2) chip selects are all asserted active, and (3) the write signals (gw , bwe ) are all deasserted high. adsp is ignored if ce 1 is high. the address presented to the address inputs is stored in the address advancement logic and the address register while being presented to the memory core. the cor- responding data is allowed to propagate to the input of the output registers. at the rising edge of the next clock the data is allowed to propagate through the output register and onto the data bus within 2.2 ns (300-mhz device) if oe is active low. the only exception occurs when the sram is emerging from a deselected state to a selected state, its outputs are always three-stated during the first cycle of the access. after the first cycle of the access, the outputs are controlled by the oe signal. consecutive single read cycles are supported. once the sram is deselected at clock rise by the chip select and either adsp or adsc signals, its output will three-state immediately. single write accesses initiated by adsp this access is initiated when both of the following conditions are satisfied at clock rise: (1) adsp is asserted low, and (2) chip select is asserted active. the address presented is load- ed into the address register and the address advancement logic while being delivered to the ram core. the write signals (gw , bwe , and bw x) and adv inputs are ignored during this first cycle. adsp triggered write accesses require two clock cycles to complete. if gw is asserted low on the second clock rise, the data presented to the dqx inputs is written into the corre- sponding address location in the ram core. if gw is high, then the write operation is controlled by bwe and bw x sig- nals. the cy7c1440v33/cy7c1442v33/cy7c1446v33 pro- vides byte write capability that is described in the write cycle description table. asserting the byte write enable input (bwe ) with the selected byte write (bw a,b,c,d for cy7c1440v33, bw a,b,c,d,e,f,g,h for cy7c1446v33, and bw a,b for cy7c1442v33) input will selectively write to only the de- sired bytes. bytes not selected during a byte write operation will remain unaltered. a synchronous self-timed write mecha- nism has been provided to simplify the write operations. because the cy7c1440v33/cy7c1442v33/cy7c1446v33 is a common i/o device, the output enable (oe ) must be deas- serted high before presenting data to the dq inputs. doing so will three-state the output drivers. as a safety precaution, dq are automatically three-stated whenever a write cycle is detected, regardless of the state of oe . single write accesses initiated by adsc adsc write accesses are initiated when the following condi- tions are satisfied: (1) adsc is asserted low, (2) adsp is deasserted high, (3) chip select is asserted active, and (4) the appropriate combination of the write inputs (gw , bwe , and bw x) are asserted active to conduct a write to the desired byte(s). adsc triggered write accesses require a single clock cycle to complete. the address presented to a [x:0] (x = 20 for cy7c1440v33, x = 21 for cy7c1442v33, and x = 19 for cy7c1446v33) is loaded into the address register and the address advancement logic while being delivered to the ram core. the adv input is ignored during this cycle. if a global write is conducted, the data presented to the dq [x:0] is written into the corresponding address location in the ram core. if a byte write is conducted, only the selected bytes are written. bytes not selected during a byte write operation will remain unaltered. a synchronous self-timed write mechanism has been provided to simplify the write operations. because the cy7c1440v33/cy7c1442v33/cy7c1446v33 is a common i/o device, the output enable (oe ) must be deas- serted high before presenting data to the dq [x:0] inputs. do- ing so will three-state the output drivers. as a safety precau- tion, dq [x:0] are automatically three-stated whenever a write cycle is detected, regardless of the state of oe . burst sequences the cy7c1440v33/cy7c1442v33/cy7c1446v33 provides a two-bit wrap around counter, fed by a [1:0] , that implements either an interleaved or linear burst sequence. the interleaved burst sequence is designed specifically to support intel ? pen- tium applications. the linear burst sequence is designed to support processors that follow a linear burst sequence. the burst sequence is user selectable through the mode input.
preliminary cy7c1440v33 cy7c1442v33 cy7c1446v33 document #: 38-05184 rev. ** page 11 of 35 asserting adv low at clock rise will automatically increment the burst counter to the next address in the burst sequence. both read and write burst operations are supported. sleep mode the zz input pin is an asynchronous input. asserting zz plac- es the sram in a power conservation ? sleep ? mode. two clock cycles are required to enter into or exit from this ? sleep ? mode. while in this mode, data integrity is guaranteed. accesses pending when entering the ? sleep ? mode are not considered valid nor is the completion of the operation guaranteed. the device must be deselected prior to entering the ? sleep ? mode. ce s, adsp , and adsc must remain inactive for the duration of t zzrec after the zz input returns low. interleaved burst sequence first address second address third address fourth address a [1:0]] a [1:0] a [1:0] a [1:0] 00 01 10 11 01 00 11 10 10 11 00 01 11 10 01 00 linear burst sequence first address second address third address fourth address a [1:0] a [1:0] a [1:0] a [1:0] 00 01 10 11 01 10 11 00 10 11 00 01 11 00 01 10 zz mode electrical characteristics parameter description test conditions min. max. unit i ddzz snooze mode standby current zz > v dd ? 0.2v 15 ma t zzs device operation to zz zz > v dd ? 0.2v 2t cyc ns t zzrec zz recovery time zz < 0.2v 2t cyc ns
preliminary cy7c1440v33 cy7c1442v33 cy7c1446v33 document #: 38-05184 rev. ** page 12 of 35 cycle descriptions [1, 2, 3, 4] next cycle add. used zz ce 3 ce 2 ce 1 adsp adsc adv oe dq write unselected none l x x 1 x 0 x x hi-z x unselected none l 1 x 0 0 x x x hi-z x unselected none l x 0 0 0 x x x hi-z x unselected none l 1 x 0 1 0 x x hi-z x unselected none l x 0 0 1 0 x x hi-z x begin read external l 0 1 0 0 x x x hi-z x begin read external l 0 1 0 1 0 x x hi-z read continue read next l x x x 1 1 0 1 hi-z read continue read next l x x x 1 1 0 0 dq read continue read next l x x 1 x 1 0 1 hi-z read continue read next l x x 1 x 1 0 0 dq read suspend read current l x x x 1 1 1 1 hi-z read suspend read current l x x x 1 1 1 0 dq read suspend read current l x x 1 x 1 1 1 hi-z read suspend read current l x x 1 x 1 1 0 dq read begin write current l x x x 1 1 1 x hi-z write begin write current l x x 1 x 1 1 x hi-z write begin write external l 0 1 0 1 0 x x hi-z write continue write next l x x x 1 1 0 x hi-z write continue write next l x x 1 x 1 0 x hi-z write suspend write current l x x x 1 1 1 x hi-z write suspend write current l x x 1 x 1 1 x hi-z write zz ? sleep ? none h x x x x x x x hi-z x notes: 1. x= ? don't care. ? 1= high, 0 = low. 2. write is defined by bwe , bw x, and gw . see write cycle descriptions table. 3. the dq pins are controlled by the current cycle and the oe signal. oe is asynchronous and is not sampled with the clock. 4. ce 1 , ce 2 , and ce 3 are available only in the tqfp package. bga package has a single chip select ce 1 .
preliminary cy7c1440v33 cy7c1442v33 cy7c1446v33 document #: 38-05184 rev. ** page 13 of 35 write cycle descriptions [5, 6, 7] function (cy7c1440v33) gw bwe bw dbw cbw bbw a read 1 1xxxx read 101111 write byte 0 ? dqa 101110 write byte 1 ? dqb 101101 write bytes 1, 0 101100 write byte 2 ? dqc 101011 write bytes 2, 0 101010 write bytes 2, 1 101001 write bytes 2, 1, 0 1 0 1 0 0 0 write byte 3 ? dqd 100111 write bytes 3, 0 100110 write bytes 3, 1 100101 write bytes 3, 1, 0 1 0 0 1 0 0 write bytes 3, 2 100011 write bytes 3, 2, 0 1 0 0 0 1 0 write bytes 3, 2, 1 1 0 0 0 0 1 write all bytes 1 0 0 0 0 0 write all bytes 0 x x x x x function (cy7c1442v33) gw bwe bw bbw a read 1 1 x x read 1 0 1 1 write byte 0 ? dq [7:0] and dp 0 1010 write byte 1 ? dq [15:8] and dp 1 1001 write all bytes 1 0 0 0 write all bytes 0 x x x
preliminary cy7c1440v33 cy7c1442v33 cy7c1446v33 document #: 38-05184 rev. ** page 14 of 35 ieee 1149.1 serial boundary scan (jtag) the cy7c1440v33/cy7c1442v33 incorporates a serial boundary scan test access port (tap) in the fbga package only. the tqfp package does not offer this functionality. this port operates in accordance with ieee standard 1149.1-1900, but does not have the set of functions required for full 1149.1 compliance. these functions from the ieee specification are excluded because their inclusion places an added delay in the critical speed path of the sram. note that the tap controller functions in a manner that does not conflict with the operation of other devices using 1149.1 fully compliant taps. the tap operates using jedec standard 3.3v i/o logic levels. disabling the jtag feature it is possible to operate the sram without using the jtag feature. to disable the tap controller, tck must be tied low (v ss ) to prevent clocking of the device. tdi and tms are inter- nally pulled up and may be unconnected. they may alternately be connected to v dd through a pull-up resistor. tdo should be left unconnected. upon power-up, the device will come up in a reset state that will not interfere with the operation of the device. test access port (tap) - test clock the test clock is used only with the tap controller. all inputs are captured on the rising edge of tck. all outputs are driven from the falling edge of tck. test mode select the tms input is used to give commands to the tap controller and is sampled on the rising edge of tck. it is allowable to leave this pin unconnected if the tap is not used. the pin is pulled up internally, resulting in a logic high level. test data-in (tdi) the tdi pin is used to serially input information into the regis- ters and can be connected to the input of any of the registers. the register between tdi and tdo is chosen by the instruc- tion that is loaded into the tap instruction register. for infor- mation on loading the instruction register, see the tap control- ler state diagram. tdi is internally pulled up and can be unconnected if the tap is unused in an application. tdi is con- nected to the most significant bit (msb) on any register. test data-out (tdo) the tdo output pin is used to serially clock data-out from the registers. the output is active depending upon the current state of the tap state machine (see tap controller state diagram). the output changes on the falling edge of tck. tdo is connected to the least significant bit (lsb) of any register. performing a tap reset a reset is performed by forcing tms high (v dd ) for five rising edges of tck. this reset does not affect the operation of the sram and may be performed while the sram is operating. at power-up, the tap is reset internally to ensure that tdo comes up in a high-z state. tap registers registers are connected between the tdi and tdo pins and allow data to be scanned into and out of the sram test circuit- ry. only one register can be selected at a time through the instruction registers. data is serially loaded into the tdi pin on the rising edge of tck. data is output on the tdo pin on the falling edge of tck. instruction register three-bit instructions can be serially loaded into the instruc- tion register. this register is loaded when it is placed between the tdi and tdo pins, as shown in the tap controller block diagram. upon power-up, the instruction register is loaded with the idcode instruction. it is also loaded with the idcode instruction if the controller is placed in a reset state as de- scribed in the previous section. when the tap controller is in the captureir state, the two least significant bits are loaded with a binary ? 01 ? pattern to allow for fault isolation of the board level serial test path. bypass register to save time when serially shifting data through registers, it is sometimes advantageous to skip certain states. the bypass register is a single-bit register that can be placed between tdi and tdo pins. this allows data to be shifted through the sram with minimal delay. the bypass register is set low (v ss ) when the bypass instruction is executed. boundary scan register the boundary scan register is connected to all the input and output pins on the sram. several no connect (nc) pins are also included in the scan register to reserve pins for higher density devices. the x36 configuration has a 70-bit-long reg- ister, and the x18 configuration has a 51-bit-long register. the boundary scan register is loaded with the contents of the ram input and output ring when the tap controller is in the capture-dr state and is then placed between the tdi and tdo pins when the controller is moved to the shift-dr state. the extest, sample/preload and sample z instruc- tions can be used to capture the contents of the input and output ring. the boundary scan order tables show the order in which the bits are connected. each bit corresponds to one of the bumps on the sram package. the msb of the register is connected to tdi, and the lsb is connected to tdo. identification (id) register the id register is loaded with a vendor-specific, 32-bit code during the capture-dr state when the idcode command is loaded in the instruction register. the idcode is hardwired into the sram and can be shifted out when the tap controller is in the shift-dr state. the id register has a vendor code and other information described in the identification register defi- nitions table. tap instruction set eight different instructions are possible with the three-bit in- struction register. all combinations are listed in the instruction code table. three of these instructions are listed as re- served and should not be used. the other five instructions are described in detail below. the tap controller used in this sram is not fully compliant to the 1149.1 convention because some of the mandatory 1149.1 instructions are not fully implemented. the tap controller can- not be used to load address, data or control signals into the
preliminary cy7c1440v33 cy7c1442v33 cy7c1446v33 document #: 38-05184 rev. ** page 15 of 35 sram and cannot preload the input or output buffers. the sram does not implement the 1149.1 commands extest or intest or the preload portion of sample/preload; rather it performs a capture of the input and output ring when these instructions are executed. instructions are loaded into the tap controller during the shift-ir state when the instruction register is placed between tdi and tdo. during this state, instructions are shifted through the instruction register through the tdi and tdo pins. to execute the instruction once it is shifted in, the tap control- ler needs to be moved into the update-ir state. extest extest is a mandatory 1149.1 instruction which is to be ex- ecuted whenever the instruction register is loaded with all 0s. extest is not implemented in the tap controller, and there- fore this device is not compliant to the 1149.1 standard. the tap controller does recognize an all-0 instruction. when an extest instruction is loaded into the instruction register, the sram responds as if a sample/preload instruction has been loaded. there is one difference between the two instructions. unlike the sample/preload instruction, extest places the sram outputs in a high-z state. idcode the idcode instruction causes a vendor-specific, 32-bit code to be loaded into the instruction register. it also places the instruction register between the tdi and tdo pins and allows the idcode to be shifted out of the device when the tap con- troller enters the shift-dr state. the idcode instruction is loaded into the instruction register upon power-up or whenever the tap controller is given a test logic reset state. sample z the sample z instruction causes the boundary scan register to be connected between the tdi and tdo pins when the tap controller is in a shift-dr state. it also places all sram outputs into a high-z state. sample/preload sample/preload is a 1149.1 mandatory instruction. the preload portion of this instruction is not implemented, so the tap controller is not fully 1149.1 compliant. when the sample/preload instruction is loaded into the instruction register and the tap controller is in the capture-dr state, a snapshot of data on the inputs and output pins is cap- tured in the boundary scan register. the user must be aware that the tap controller clock can only operate at a frequency up to 10 mhz, while the sram clock operates more than an order of magnitude faster. because there is a large difference in the clock frequencies, it is possible that during the capture-dr state, an input or output will under- go a transition. the tap may then try to capture a signal while in transition (metastable state). this will not harm the device, but there is no guarantee as to the value that will be captured. repeatable results may not be possible. to guarantee that the boundary scan register will capture the correct value of a signal, the sram signal must be stabilized long enough to meet the tap controller ? s capture set-up plus hold times (t cs and t ch ). the sram clock input might not be captured correctly if there is no way in a design to stop (or slow) the clock during a sample/preload instruction. if this is an issue, it is still possible to capture all other signals and simply ignore the value of the ck and ck captured in the boundary scan register. once the data is captured, it is possible to shift out the data by putting the tap into the shift-dr state. this places the bound- ary scan register between the tdi and tdo pins. note that since the preload part of the command is not implemented, putting the tap into the update to the update-dr state while performing a sample/preload in- struction will have the same effect as the pause-dr command. bypass when the bypass instruction is loaded in the instruction reg- ister and the tap is placed in a shift-dr state, the bypass register is placed between the tdi and tdo pins. the advan- tage of the bypass instruction is that it shortens the boundary scan path when multiple devices are connected together on a board. reserved these instructions are not implemented but are reserved for future use. do not use these instructions.
preliminary cy7c1440v33 cy7c1442v33 cy7c1446v33 document #: 38-05184 rev. ** page 16 of 35 tap controller state diagram test-logic reset test-logic/ idle select dr-scan capture-dr shift-dr exit1-dr pause-dr exit2-dr update-dr select ir-scan capture-dr shift-ir exit1-ir pause-ir exit2-ir update-ir 1 0 1 1 0 1 0 1 0 0 0 1 1 1 0 1 0 1 0 0 0 1 0 1 1 0 1 0 0 1 1 note: the 0/1 next to each state represents the value at tms at the rising edge of tck.
preliminary cy7c1440v33 cy7c1442v33 cy7c1446v33 document #: 38-05184 rev. ** page 17 of 35 tap controller block diagram 0 0 1 2 . . 29 30 31 boundary scan register identification register 0 1 2 . . . . . 0 1 2 instruction register bypass register selection circuitry selection circuitry tap controller tdi tdo tck tms tap electrical characteristics over the operating range [5, 6] parameter description test conditions min. max. unit v oh1 output high voltage i oh = ? 4.0 ma 2.4 v v oh2 output high voltage i oh = ? 100 a 3.0 v v ol1 output low voltage i ol = 8.0 ma 0.4 v v ol2 output low voltage i ol = 100 a 0.2 v v ih input high voltage 1.8 v dd + 0.3 v v il input low voltage ? 0.5 0.8 v i x input load current gnd v i v ddq ? 5 5 a notes: 5. all voltage referenced to ground. 6. overshoot: v ih (ac) < v dd + 1.5v for t < t tcyc /2, undershoot:v il (ac) < 0.5v for t < t tcyc /2, power-up: v ih < 2.6v and v dd < 2.4v and v ddq < 1.4v for t < 200 ms.
preliminary cy7c1440v33 cy7c1442v33 cy7c1446v33 document #: 38-05184 rev. ** page 18 of 35 tap ac switching characteristics over the operating range [7, 8] parameters description min. max unit t tcyc tck clock cycle time 100 ns t tf tck clock frequency 10 mhz t th tck clock high 40 ns t tl tck clock low 40 ns set-up times t tmss tms set-up to tck clock rise 10 ns t tdis tdi set-up to tck clock rise 10 ns t cs capture set-up to tck rise 10 ns hold times t tmsh tms hold after tck clock rise 10 ns t tdih tdi hold after clock rise 10 ns t ch capture hold after clock rise 10 ns output times t tdov tck clock low to tdo valid 20 ns t tdox tck clock low to tdo invalid 0 ns notes: 7. t cs and t ch refer to the set-up and hold time requirements of latching data from the boundary scan register. 8. test conditions are specified using the load in tap ac test conditions. t r /t f = 1 ns.
preliminary cy7c1440v33 cy7c1442v33 cy7c1446v33 document #: 38-05184 rev. ** page 19 of 35 tap timing and test conditions (a) tdo c l = 20 pf z 0 = 50 ? gnd 1.25v 50 ? v ih 0v all input pulses test clock test mode select tck tms test data-in tdi test data-out t tc yc t tmsh t tl t th t tmss t tdis t tdih t td ov t tdo x tdo
preliminary cy7c1440v33 cy7c1442v33 cy7c1446v33 document #: 38-05184 rev. ** page 20 of 35 identification register definitions instruction field x 18 x36 description revision number (31:29) 000 000 reserved for version number. department number (27:25) 101 101 department number voltage (28&24) 00 00 architecture (23:21) 000 000 architecture type memory type (20:18) 000 000 defines type of memory device width (17:15) 010 100 defines width of the sram. x36 or x18 device density (14:12) 111 111 defines the density of the sram cypress jedec id (11:1) 00011100100 00011100100 allows unique identification of sram vendor. id register presence (0) 1 1 indicate the presence of an id register. scan register sizes register name bit size (x18) bit size (x36) instruction 3 3 bypass 1 1 id 32 32 boundary scan 51 70 identification codes instruction code description extest 000 captures the input/output ring contents. places the boundary scan register between the tdi and tdo. forces all sram outputs to high-z state. this instruction is not 1149.1 compliant. idcode 001 loads the id register with the vendor id code and places the register be- tween tdi and tdo. this operation does not affect sram operation. sample z 010 captures the input/output contents. places the boundary scan register be- tween tdi and tdo. forces all sram output drivers to a high-z state. reserved 011 do not use: this instruction is reserved for future use. sample/preload 100 captures the input/output ring contents. places the boundary scan register between tdi and tdo. does not affect the sram operation. this instruction does not implement 1149.1 preload function and is therefore not 1149.1 compliant. reserved 101 do not use: this instruction is reserved for future use. reserved 110 do not use: this instruction is reserved for future use. bypass 111 places the bypass register between tdi and tdo. this operation does not affect sram operation.
preliminary cy7c1440v33 cy7c1442v33 cy7c1446v33 document #: 38-05184 rev. ** page 21 of 35 boundary scan order (1m x 36) bit # signal name bump id bit # signal name bump id boundary scan order (2m x 18) bit # signal name bump id bit # signal name bump id
preliminary cy7c1440v33 cy7c1442v33 cy7c1446v33 document #: 38-05184 rev. ** page 22 of 35 maximum ratings (above which the useful life may be impaired. for user guide- lines, not tested.) storage temperature ................................. ? 55 c to +150 c ambient temperature with power applied............................................. ? 55 c to +125 c supply voltage on v dd relative to gnd ....... ? 0.3v to +4.6v dc voltage applied to outputs in high z state [9] ................................. ? 0.5v to v ddq + 0.5v dc input voltage [9] ............................. ? 0.5v to v ddq + 0.5v current into outputs (low) ........................................ 20 ma static discharge voltage .......................................... >2001v (per mil-std-883, method 3015) latch-up current.................................................... >200 ma operating range range ambient temp. [10] v dd v ddq com ? l 0 c ? 70 c 3.3v 5% 2.375v (min.) v dd (max.) electrical characteristics over the operating range parameter description test conditions min. max. unit v dd power supply voltage 3.135 3.465 v v ddq i/o supply voltage 2.375 v dd v v oh output high voltage v dd = min., i oh = ? 4.0 ma v ddq = 3.3v 2.4 v v dd = min., i oh = ? 1.0 ma v ddq = 2.5v 2.0 v v ol output low voltage v dd = min., i ol = 8.0 ma v ddq = 3.3v 0.4 v v dd = min., i ol = 1.0 ma v ddq = 2.5v 0.4 v v ih input high voltage v ddq = 3.3v 2.0 v v ddq = 2.5v 1.7 v v il input low voltage [9] v ddq = 3.3v ? 0.3 0.8 v v ddq = 2.5v ? 0.3 0.7 v i x input load current gnd v i v ddq 5 a input current of mode 30 a i oz output leakage current gnd v i v ddq, output disabled 5 a i dd v dd operating supply v dd = max., i out = 0 ma, f = f max = 1/t cyc 300 mhz tbd ma 250 mhz tbd ma 200 mhz tbd ma 166 mhz tbd ma i sb1 automatic ce power-down current ? ttl inputs max. v dd , device deselected, v in > v ih or v in < v il f = f max = 1/t cyc 300 mhz tbd ma 250 mhz tbd ma 200 mhz tbd ma 166 mhz tbd ma i sb2 automatic ce power-down current ? cmos inputs max. v dd , device deselected, v in 0.3v or v in > v ddq ? 0.3v, f = 0 all speed grades tbd ma i sb3 automatic ce power-down current ? cmos inputs max. v dd , device deselected, or v in 0.3v or v in > v ddq ? 0.3v f = f max = 1/t cyc 300 mhz tbd ma 250 mhz tbd ma 200 mhz tbd ma 166 mhz tbd ma i sb4 automatic ce power-down current ? ttl inputs max. v dd , device deselected, v in v ih or v in v il , f = 0 all speed grades tbd ma shaded areas contain advance information. notes: 9. minimum voltage equals ? 2.0v for pulse durations of less than 20 ns 10. t a is the temperature.
preliminary cy7c1440v33 cy7c1442v33 cy7c1446v33 document #: 38-05184 rev. ** page 23 of 35 capacitance [11] parameter description test conditions max. unit c in input capacitance t a = 25 c, f = 1 mhz, v dd = 3.3v, v ddq = 2.5v tbd pf c clk clock input capacitance tbd pf c i/o input/output capacitance tbd pf ac test loads and waveforms [12] notes: 11. tested initially and after any design or process changes that may affect these parameters. 12. input waveform should have a slew rate of 1 v/ns. output r = 317 ? r = 351 ? 5pf including jig and scope (a) (b) output r l = 50 ? z 0 = 50 ? v th = 1.5v v ddq all input pulses vdd gnd 90% 10% 90% 10% 1 v/ns 1 v/ns (c)
preliminary cy7c1440v33 cy7c1442v33 cy7c1446v33 document #: 38-05184 rev. ** page 24 of 35 switching characteristics over the operating range [13, 14, 15] -300 -250 -200 -167 parameter description min. max. min. max. min. max. min. max. unit t cyc clock cycle time 3.3 4.0 5.0 6.0 ns t ch clock high 1.5 1.5 2.0 2.4 ns t cl clock low 1.5 1.5 2.0 2.4 ns t as address set-up before clk rise 1.5 1.5 1.5 1.5 ns t ah address hold after clk rise 0.5 0.5 0.5 0.5 ns t co data output valid after clk rise 2.3 2.7 3.0 3.5 ns t doh data output hold after clk rise 1.5 1.5 1.5 1.5 ns t ads adsp , adsc set-up before clk rise 1.5 1.5 1.5 1.5 ns t adh adsp , adsc hold after clk rise 0.5 0.5 0.5 0.5 ns t wes bwe , gw , bw x set-up before clk rise 1.5 1.5 1.5 1.5 ns t weh bwe , gw , bw x hold after clk rise 0.5 0.5 0.5 0.5 ns t advs adv set-up before clk rise 1.5 1.5 1.5 1.5 ns t advh adv hold after clk rise 0.5 0.5 0.5 0.5 ns t ds data input set-up before clk rise 1.5 1.5 1.5 1.5 ns t dh data input hold after clk rise 0.5 0.5 0.5 0.5 ns t ces chip enable set-up 1.5 1.5 1.5 1.5 ns t ceh chip enable hold after clk rise 0.5 0.5 0.5 0.5 ns t chz clock to high-z [14] 2.3 2.3 3.0 3.0 ns t clz clock to low-z [14] 1.5 1.5 1.5 1.5 ns t eohz oe high to output high-z [14, 15] 2.3 2.3 3.0 3.0 ns t eolz oe low to output low-z [14, 15] 0 0 0 0 ns t eov oe low to output valid [14] 2.3 2.7 3.0 3.5 ns notes: 13. unless otherwise noted, test conditions assume signal transition time of 2.5 ns or less, timing reference levels of 1.25v, i nput pulse levels of 0 to 2.5v, and output loading of the specified i ol /i oh and load capacitance. shown in (a), (b) and (c) of ac test loads. 14. t chz , t clz , t oev , t eolz , and t eohz are specified with a load capacitance of 5 pf as in part (b) of ac test loads. transition is measured 200 mv from steady-state voltage. 15. at any given voltage and temperature, t eohz is less than t eolz and t chz is less than t clz .
preliminary cy7c1440v33 cy7c1442v33 cy7c1446v33 document #: 38-05184 rev. ** page 25 of 35 1 switching waveforms write cycle timing [4, 16, 17] notes: 16. we is the combination of bwe , bw x, and gw to define a write cycle (see write cycle descriptions table). 17. wdx stands for write data to address x. adsp clk adsc adv add ce 1 oe gw we ce 2 ce 3 1a data in t cyc t ch t cl t ads t adh t ads t adh t advs t advh wd1 wd2 wd3 t ah t as t ws t wh t wh t ws t ces t ceh t ces t ceh t ces t ceh 2b 3a 1a single write burst write unselected adsp ignored with ce 1 inactive ce 1 masks adsp = don ? t care = undefined pipelined write 2a 2c 2d t dh t ds high-z high-z unselected with ce 2 adv must be inactive for adsp write adsc initiated write
preliminary cy7c1440v33 cy7c1442v33 cy7c1446v33 document #: 38-05184 rev. ** page 26 of 35 read cycle timing [4, 16, 18] note: 18. rdx stands for read data from address x. switching waveforms (continued) adsp clk adsc adv add ce 1 oe gw we ce 2 ce 3 2a 2c 1a data out t cyc t ch t cl t ads t adh t ads t adh t advs t advh rd1 rd2 rd3 t ah t as t ws t wh t wh t ws t ces t ceh t ces t ceh t ces t ceh t co t eov 2b 2c 2d 3a 1a t oehz t doh t clz t chz single read burst read unselected adsp ignored with ce 1 inactive suspend burst ce 1 masks adsp = don ? t care = undefined pipelined read adsc initiated read unselected with ce 2
preliminary cy7c1440v33 cy7c1442v33 cy7c1446v33 document #: 38-05184 rev. ** page 27 of 35 read/write cycle timing [4, 16, 17, 18] notes: 19. device originally deselected. 20. ce is the combination of ce 2 and ce 3 . all chip selects need to be active in order to select the device. switching waveforms (continued) adsp clk adsc adv add ce 1 oe gw we ce 2 ce 3 1a data in/out t cyc t ch t cl t ads t adh t ads t adh t advs t advh rd1 wd2 rd3 t ah t as t ws t wh t wh t ws t ces t ceh t ces t ceh t ces t ceh t eolz t co t eov 3a 3c 3d 1a t eohz t doh t chz single read burst read unselected adsp ignored with ce 1 inactive ce 1 masks adsp = don ? t care = undefined pipelined read out 2a in 3b out out out out single write t ds t dh 2a out
preliminary cy7c1440v33 cy7c1442v33 cy7c1446v33 document #: 38-05184 rev. ** page 28 of 35 switching waveforms (continued) oe three-state i/os t eohz t eov t eolz oe switching waveforms
switching waveforms (continued) adsp clk adsc ce 1 ce 3 low high zz t zzs t zzrec i dd i dd (active) three-state i/os notefjdfdhfdjfdfjdjdjdjno notes: 21. device must be deselected when entering zz mode. see cycle descriptions table for all possible signal conditions to deselect the device. 22. i/os are in three-state when exiting zz sleep mode. zz mode timing [4, 21, 22] ce 2 i ddzz high
preliminary cy7c1440v33 cy7c1442v33 cy7c1446v33 document #: 38-05184 rev. ** page 30 of 35 ordering information speed (mhz) ordering code package name package type operating range 300 cy7c1440v33-300ac cy7c1442v33-300ac a101 100-lead 14 x 20 x 1.4 mm thin quad flat pack commercial cy7c1440v33-300bgc cy7c1442v33-300bgc bg119 119-ball bga (14 x 22 x 2.4 mm) cy7c1446v33-300bx bg209 209-ball fbga (14 x 22 x 2.2mm) cy7c1440v33-300bzc cy7c1442v33-300bzc bb165b 165-ball fbga (15 x 17 mm) 250 cy7c1440v33-250ac cy7c1442v33-250ac a101 100-lead 14 x 20 x 1.4 mm thin quad flat pack cy7c1440v33-250bgc cy7c1442v33-250bgc bg119 119-ball bga (14 x 22 x 2.4 mm) cy7c1446v33-250bx bg209 209-ball fbga (14 x 22 x 2.2mm) cy7c1440v33-250bzc cy7c1442v33-250bzc bb165b 165-ball fbga (15 x 17 mm) 200 cy7c1440v33-200ac cy7c1442v33-200ac a101 100-lead 14 x 20 x 1.4 mm thin quad flat pack cy7c1440v33-200bgc cy7c1442v33-200bgc bg119 119-ball bga (14 x 22 x 2.4 mm) cy7c1446v33-200bx bg209 209-ball fbga (14 x 22 x 2.2mm) cy7c1440v33-200bzc CY7C1442V33-200BZC bb165b 165-ball fbga (15 x 17 mm) 167 cy7c1440v33-167ac cy7c1442v33-167ac a101 100-lead 14 x 20 x 1.4 mm thin quad flat pack cy7c1440v33-167bgc cy7c1442v33-167bgc bg119 119-ball bga (14 x 22 x 2.4 mm) cy7c1446v33-167bx bg209 209-ball fbga (14 x 22 x 2.2mm) cy7c1440v33-167bzc cy7c1442v33-167bzc bb165b 165-ball fbga (15 x 17 mm) shaded areas contain advance information.
preliminary cy7c1440v33 cy7c1442v33 cy7c1446v33 document #: 38-05184 rev. ** page 31 of 35 package diagrams 100-pin thin plastic quad flatpack (14 x 20 x 1.4 mm) a101 51-85050-a
preliminary cy7c1440v33 cy7c1442v33 cy7c1446v33 document #: 38-05184 rev. ** page 32 of 35 package diagrams (continued) 165-ball fbga (13 x 15 x 1.62 mm) bb165b 51-49026-**
preliminary cy7c1440v33 cy7c1442v33 cy7c1446v33 document #: 38-05184 rev. ** page 33 of 35 package diagrams (continued) 119-lead pbga (14 x 22 x 2.4 mm) bg119 51-85115-*a
preliminary cy7c1440v33 cy7c1442v33 cy7c1446v33 document #: 38-05184 rev. ** page 34 of 35 ? cypress semiconductor corporation, 2002. the information contained herein is subject to change without notice. cypress semico nductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress semiconductor product. nor does it convey or imply any license unde r patent or other rights. cypress semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected t o result in significant injury to the user. the inclusion of cypress semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in do i ng so indemnifies cypress semiconductor against all charges. no bus latency and nobl are trademarks of cypress semiconductor corporation. zbt is a trademark of integrated device technology. all product and company names mentioned in this document may be the trademarks of their respective holders. package diagrams (continued) 209-lead pbga (14 x 22 x 2.20 mm) bg209 51-85143-*a
preliminary cy7c1440v33 cy7c1442v33 cy7c1446v33 document #: 38-05184 rev. ** page 35 of 35 document title: cy7c1440v33, cy7c1442v33, cy7c1446v33 1m x 36 / 2m x 18 / 512k x 72 pipelined sram document number: 38-05184 rev. ecn no. issue date orig. of change description of change ** 113761 04/11/02 pks 1. new datasheet

▲Up To Search▲

Price & Availability of CY7C1442V33-200BZC

	To Download CY7C1442V33-200BZC Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .